Ka / Ku-band beamformer chips.
Connecting ground terminals to a world beyond.
| Specification | Value |
|---|---|
| TX Band | 27.5–31 GHz |
| TX Channels | 8 |
| TX Gain | 23 dB |
| TX OP1dB | 17 dBm typical |
| TX Power | 280 mW/channel @ 17 dBm |
| Phase Control | 6-bit; 5.625° step; 360° range |
| Attenuator | 5-bit; 0.5 dB step; 15.5 dB range |
| Supply | 1.8 V / 2.5 V |
| Package | 4.4 × 4.9 mm FC-BGA |
| Specification | Value |
|---|---|
| RX Band | 17.7–21.2 GHz |
| RX Channels | 8 |
| RX Gain | 25 dB typical |
| RX Noise Figure | 1.8 dB typ / 1.9 dB max |
| RX Input P1dB | −38 dBm typical |
| RX Power | 320 mW all 8; 40 mW/ch avg |
| Phase Control | 6-bit; 5.625° step; 360° range |
| Attenuator | 5-bit; 0.5 dB step; 15.5 dB range |
| Supply / Package | 1.2 V RF; 2.5 V analog/digital; 4.4 × 4.9 mm FC-BGA |
| Specification | RX | TX |
|---|---|---|
| Band | 10.7–12.7 GHz | 14–14.5 GHz |
| RF Ports | 4 RX ports | 4 TX ports |
| Operating Mode | TDD half-duplex | TDD half-duplex |
| Gain | 21 dB typical | 27 dB typical |
| P1dB | Input: −38 dBm typ | Output: 11 dBm typ |
| Power | 40 mW/channel | 55 mW/channel |
| Phase Shifter | 6-bit; 5.625° step; 360° range | 6-bit; 5.625° step; 360° range |
| Attenuator | 6-bit; 0.5 dB step; 23.5 dB range | 6-bit; 0.5 dB step; 23.5 dB range |
| Package | 4.8 × 4.8 mm FC-BGA | 4.8 × 4.8 mm FC-BGA |
| Specification | RX | TX |
|---|---|---|
| Band | 10.5–15 GHz | 10.5–15 GHz |
| Channels | 16 RX channels | 16 TX channels |
| Gain | 10 dB min / 12 dB typ (SPG) | 6 dB typ |
| Noise Figure | 10 dB / 12 dB max | — |
| Power | 30 mW/channel | 30 mW/channel |
| Phase Control | 6-bit; 5.625° step; 360° | 6-bit; 5.625° step; 360° |
| Attenuator | 6-bit; 0.5 dB; 31.5 dB range | 6-bit; 0.5 dB; 31.5 dB range |
| Settling Time | 20 ns typical | 20 ns typical |
| Supply | 1.2 V RF/PA | 2.5 V analog/digital |
| Package | 6.8 × 7.8 mm FC-CSP, 186-pin | 6.8 × 7.8 mm FC-CSP, 186-pin |
| Specification | RX | TX |
|---|---|---|
| Band | 10.5–13 GHz | 13–15 GHz |
| Channels | 2 bidirectional channels | 2 bidirectional channels |
| Gain | 29 dB typical | 32 dB typical |
| Noise Figure | 1.3 dB typical | — |
| P1dB | Input: −26 dBm typ | Output: 10.5 dBm typ |
| Power | 20 mW/channel | 45 mW/channel |
| Switching | 40 ns min / 60 ns typ | 80 ns min / 100 ns typ |
| Supply | 1.6–2.0 V (1.8 V typ) | 1.6–2.0 V (1.8 V typ) |
| Package | 3.1 × 2.6 mm FC-CSP | 3.1 × 2.6 mm FC-CSP |
| Path / channels | RX · 8 channels | TX · 8 channels |
|---|---|---|
| RF band | 1.5–4.5 GHz | 1.9–4.5 GHz |
| Converter | Sigma-delta ADC; up to 2 GSPS; 16× OS | 12-bit DAC; up to 500 MHz sample rate |
| Bandwidth | 1–100 MHz tunable; up to 100 MHz complex | 1–100 MHz channel bandwidth |
| Gain / output | RX gain 40 dB | TX output 4 dBm |
| Noise / OIP3 | NF <15 dB; OIP3 35 dBm | TX OIP3 15 dBm |
| Image rejection | 45 dBc | 50 dBc |
| Gain / attenuation | RX gain range 40 dB | TX attenuation 0–36 dB |
| LO leakage | — | ≤−43 dBm @ 4 dBm output |
| Power / sync | <0.13 W per active channel in FDD; multi-chip sync | <0.13 W per active channel in FDD; multi-chip sync |
| Data interface | JESD204B/C; up to 33 Gbps | JESD204B/C; up to 33 Gbps |
| Package | 13 × 13 mm; 225-pin BGA | 13 × 13 mm; 225-pin BGA |
| Specification | ADC / RX | DAC / TX |
|---|---|---|
| Converter | 8 × 14-bit; 4 GSPS | 8 × 14-bit; 12 GSPS |
| RF range | 10 MHz–6 GHz input | 10 MHz–6 GHz output |
| Instantaneous BW | Up to 1.6 GHz complex | Up to 1.6 GHz complex |
| Real-signal mode | Up to 2 GHz; digital channel bypass | 2 channels; up to 6 GHz |
| Gain control | SHA fixed 6 dB; DSA 0 to −23.5 dB | — |
| Clock / interface | <50 fs RMS jitter; 60–750 MHz ref clock | JESD204B/C; 4.15–33 Gbps SerDes |
| Power | 2.5 V / 1.3 V; <1 W, 1 RX + 1 TX full-power TDD | 2.5 V / 1.3 V; <1 W, 1 RX + 1 TX full-power TDD |
| Package | 25 × 25 mm BGA; 0.8 mm pitch | 25 × 25 mm BGA; 0.8 mm pitch |
| Specification | RX | TX |
|---|---|---|
| Channels / beams | 128 / 128 @ ≤31.25 MSPS; 64 / 64 @ ≤62.5 MSPS | 96 / 32 @ ≤31.25 MSPS; 32 / 32 @ ≤62.5 MSPS |
| Sampling rate | ≤31.25 MSPS (128/128); ≤62.5 MSPS (64/64) | ≤31.25 MSPS (96/32); ≤62.5 MSPS (32/32) |
| Baseband / beam data | 12-bit input → 16-bit output | 12-bit input → 16-bit output |
| Interface / switching | JESD204B Subclass 1, ≤10 Gbps; LVDS/SPI; ping-pong <5 ns | JESD204B Subclass 1, ≤10 Gbps; LVDS/SPI; ping-pong <5 ns |
| Radiation / package | TID 100 krad (Si); SEL 75 MeV·cm²/mg; 25 × 25 mm BGA, 900-pin | TID 100 krad (Si); SEL 75 MeV·cm²/mg; 25 × 25 mm BGA, 900-pin |
| Specification | RX | TX |
|---|---|---|
| Scaling | 8/8 @ ≤1,650; 16/16 @ ≤825; 32/32 @ ≤312.5; 64/64 @ ≤156.25 MSPS | 8 ch/4 beams @ ≤1,650; 16/4 @ ≤825 or 625; 32/4 @ ≤312.5; 64/4 @ ≤156.25 MSPS |
| Array / weights | Non-cascaded full RX: 16 / 16 @ ≤1,650 MSPS | 8/8 @ ≤1,650; 16/16 @ ≤825 or 625; 32/32 @ ≤312.5; 64/64 @ ≤156.25 MSPS |
| Bandwidth / method | 1.32 GHz @ 1.65 GSPS | True time delay + complex weights |
| Switching / interface | <5 ns; JESD204B/C GTA/GTS + control interface | <5 ns; JESD204B/C GTA/GTS + control interface |
| Power / package | 1.0 V / 1.8 V / 2.0 V; 33 × 33 mm BGA, 1,024-pin | 1.0 V / 1.8 V / 2.0 V; 33 × 33 mm BGA, 1,024-pin |
| Specification | RX | TX |
|---|---|---|
| Channels | 2 RX | 2 TX + 1 observation |
| Frequency | 30 MHz–7 GHz (TDD / FDD) | 30 MHz–7 GHz (TDD / FDD) |
| Bandwidth | Tunable channel bandwidth 20 kHz–75 MHz | Tunable channel bandwidth 20 kHz–75 MHz |
| Gain / power | RX gain 30 dB | Output 5 dBm; attenuation 0–36 dB |
| Noise / OIP3 | NF 16 dB; OIP3 40 dBm | OIP3 25 dBm |
| Image / leakage | Image rejection 60 dBc | Image rejection 60 dBc; LO leakage −60 dBm |
| Signal processing / LO / hopping | Fractional-N PLL; external LO supported | 5 LO synthesizers; up to 40,000 hops/s |
| Power / package | 2.5 V / 1.3 V; <1 W (one RX + one TX, full-power TDD) | 2.5 V / 1.3 V; <1 W (one RX + one TX, full-power TDD) |
| Interface | RBDP / LVDS data; SPI / GPIO control | RBDP / LVDS data; SPI / GPIO control |
| Package | 15 × 15 mm BGA, 289-pin | 15 × 15 mm BGA, 289-pin |
Ka-band high-performance architecture
Frequency bands, model names, use cases and advantage statements follow the supplied architecture graphic. System performance claims and all RF / digital interfaces remain subject to verification against the target configuration and chip datasheets.
Designed to preserve weak signals on the receive path.
Efficient RF architecture for lower terminal power demand.
Target pricing around 50% of mainstream comparable solutions.
Years of RF development shape our next chapter in SATCOM: practical chip design, architecture and manufacturing collaboration.
Our experience spans 4G and 5G development through to satellite communications. It covers RF chip design, system and architecture design, process integration and production planning. We work with our manufacturing ecosystem to support dependable access to production capacity.
Foundry support is primarily through STMicroelectronics and GlobalFoundries, aligned with process and production planning.
Exploring a Ka- or Ku-band ground terminal? Contact AIE to discuss your architecture and integration requirements.
